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White Electronic Designs
W3EG7264S-JD3-D3
PRELIMINARY*
512MB - 64Mx72 DDR SDRAM UNBUFFERED
FEATURES
Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 * JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V JEDEC standard 184 pin DIMM package * PCB Height: 30.48mm (1.20") Max
* This product is under development, is not qualified or characterized and is subject to change without notice.
DESCRIPTION
The W3EG7264S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
NOTE: Consult Factory for availability of: * Lead-Free Products * Vendor source control options * Industrial Temperature option
OPERATING FREQUENCIES
DDR400 @CL=3 Clock Speed CL-tRCD-tRP 200MHz 3-3-3 DDR333 @CL=2.5 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2
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W3EG7264S-JD3-D3
PRELIMINARY
PIN CONFIGURATION
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DQM0 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DQM1 VCC DQ14 DQ15 NC VCCQ NC DQ20 A12 VSS DQ21 A11 DQM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DQM3 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS DQM8 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DQM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# NC DQM5 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DQM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DQM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD A0-A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC
PIN NAMES
Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect
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FUNCTIONAL BLOCK DIAGRAM
CS0# DQS0 DQM0 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQM5 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQM6 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQM7 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS#
W3EG7264S-JD3-D3
PRELIMINARY
DQS4 DQM4 DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DQS
DQS
DQS
DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
CS#
DQS SCL WP
SERIAL PD SDA A0 SA0 A1 SA1 A2 SA2
VCCSPD RAS# CAS# BA0-BA1 WE# A0-A12 CKE0 RAS: DDR SDRAMs CAS: DDR SDRAMs BA0-BA1: DDR SDRAMs WE#: DDR SDRAMs A0-A12: DDR SDRAMs CLOCK INPUT CKE0: DDR SDRAMs CK0, CK0# CK1, CK1# 3 SDRAMS 3 SDRAMS 3 SDRAMS VCCQ VCC VREF VSS
SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs DDR SDRAMs
NOTES: All resistor values are 22 ohms unless otherwise specified.
CK2, CK2#
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current
Note:
W3EG7264S-JD3-D3
PRELIMINARY
Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS
Value -0.5 to 3.6 -1.0 to 3.6 -55 to +150 9 50
Units V V C W mA
Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability
0C TA 70C; DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCCQ VREF VTT VIH VIL VOH VOL Min 2.3 2.3 1.15 1.15 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 1.35 1.35 VCCQ + 0.3 VREF -0.15 -- VTT-0.76 Unit V V V V V V V V
DC CHARACTERISTICS
CAPACITANCE
TA = 25C. f = 1MHz; DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0, CKE1) Input Capacitance (CK0#,CK0) Input Capacitance (CS0#, CS1#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT Max 32 32 32 32 32 8 32 8 8 Unit pF pF pF pF pF pF pF pF pF
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W3EG7264S-JD3-D3
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V Includes DDR SDRAM component only DDR400@ CL=3 Max DDR333@ CL=2.5 Max DDR266@ CL=2 Max DDR266@ CL=2.5 Max DDR200@ CL=2 Max
Parameter Operating Current
Symbol Conditions IDD0 One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; PowerDown mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands.
Units
1395
1170
1170
1170
1170
mA
Operating Current
IDD1
1665
1440
1440
1440
1440
mA
Precharge PowerDown Standby Current Idle Standby Current
IDD2P IDD2F
45
45
45
45
45
rnA
495
405
405
405
405
mA
Active Power-Down Standby Current Active Standby Current
IDD3P IDD3N
405
315
315
315
315
mA
540
450
450
450
450
mA
Operating Current
IDD4R
1710
1485
1485
1485
1485
mA
Operating Current
IDD4W
1758
1575
1575
1575
1575
rnA
Auto Refresh Current Self Refresh Current Operating Current
IDD5 IDD6 IDD7A
3105 45
2610 45
2610 45
2610 45
2610 45
mA mA
4050
3645
3645
3645
3645
mA
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W3EG7264S-JD3-D3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
1. 2. 3. Typical Case : DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V Worst Case : VCC=2.7V, T=10C Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRCD=15*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst *
IDD7A : OPERATING CURRENT : FOUR BANKS
1. 2. 3. Typical Case : DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V Worst Case : VCC=2.7V, T=10C Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA Timing Patterns : * DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst DDR400 (200MHz, CL=3) : tCK=5ns, BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst
4.
4.
*
*
*
*
*
*
* Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3
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W3EG7264S-JD3-D3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V AC Characteristics Parameter Access window of DQs from CK, CK# CK high-level width CK low-level width Clock cycle time CL=3 CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK, CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK, CK# Data-out low-impedance window from CK, CK# Address and control input hold time (fast slew rate) Address and control input set-up time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period Symbol tAC tCH tCL tCK (3) tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHf tISf tIHs tISs tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC 40 15 55 70 -0.70 0.60 0.60 0.60 0.60 2.2 10 tHP-tQHS 0.50 70,000 42 15 60 72 0.72 0.2 0.2 tCH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 tHP-tQHS 0.55 70,000 40 15 60 75 Min -0.70 0.45 0.45 5 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 0.40 1.28 0.75 0.2 0.2 tCH, tCL +0.70 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 45 20 65 75 +0.60 403 Max +0.70 0.55 0.55 7.5 13 13 6 7.5 0.40 0.40 1.75 -0.60 0.35 0.35 0.45 1.25 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 +0.60 13 13 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 13 13 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 13 13 Min -0.70 0.45 0.45 335 Max +0.70 0.55 0.55 262/265 Min -0.75 0.45 0.45 Max +0.75 0.55 0.55 Min -0.75 0.45 0.45 202 Max +0.75 0.55 0.55 Units ns tCK tCK ns ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 15 13,14 18 8,19 8,20 6 6 6 6 13,14 16 16 22 22 22 14,17 14,17 17 Notes
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W3EG7264S-JD3-D3
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued)
DDR333, 266, 200: VCC = VCCQ = +2.5V 0.2V; DDR400: VCC = VCCQ = +2.6V 0.1V AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Symbol tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFI tVTD tXSNR tXSRD 0 70 200 Min 15 15 0.9 0.4 10 0.25 0 0.4 15 2 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 403 Max Min 15 15 0.9 0.4 12 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 335 Max 262/265 Min 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 Max Min 20 20 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0.6 1.1 0.6 202 Max Units ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK 13 12 12 10,11 9 Notes
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Notes
1. 2. All voltages referenced to VSS Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. Outputs are measured with equivalent load: 12. 11.
W3EG7264S-JD3-D3
PRELIMINARY
It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x8 = DQS with DQ0-DQ7. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns, functionality is uncertain. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands).
3.
VTT TT 50 Reference Point 30pF
Output (VOUT (VOUT)
13.
4.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). For slew rates less than 1V/ns and greater than or equal to 0.5V/ ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. For 403 and 335, slew rates must be greater than or equal to 0.5V/ns. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VCCQ is recognized as LOW. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). The intent of the "Don't Care" state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or high-Z, and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIHDC (MIN) then it must not transition LOW (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround.
14. 15.
5.
16. 17.
6.
18. 19.
7.
8.
20. 21.
9.
22.
10.
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ORDERING INFORMATION FOR JD3
Part Number W3EG7264S403JD3 W3EG7264S335JD3 W3EG7264S263JD3 W3EG7264S265JD3 W3EG7264S202JD3 Speed 200MHz/400Mb/s 166MHz/333Mb/s 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 3 2.5 2 2.5 2
W3EG7264S-JD3-D3
PRELIMINARY
tRCD 3 3 3 3 2
tRP 3 3 3 3 2
Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") 30.48 (1.20")
NOTES: * Consult Factory for availability of Lead-Free products. (F = Lead-Free, G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR JD3
282
3.99 (0.157 (2x))
17.78 (0.700) 10.01 (0.394)
ded en mm gns eco esi ot R ew D N rN Fo
133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 6.35 (0.250) 64.77 (2.550) 6.35 (0.250) 49.53 (1.950) 1.27 (0.050 TYP.) 1.78 (0.070)
2.54 (0.100)
30.48 (1.20) MAX
3.99 (0.157) (MIN)
WEDC
2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004)
* All Dimensions are in millimeters and (inches)
May 2005 Rev. 5
10
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
512MB - 64Mx72 DDR SDRAM UNBUFFERED
W3EG7264S-JD3-D3
PRELIMINARY
Revision History Rev #
Rev 0 Rev 1 Rev 2
History
Created Datasheet Corrected Mechanical Drawing 2.1 Added document title page 2.2 Removed "ED" for Part Marking
Release Date
3-6-02 1-30-03 4-27-04
Status
Advanced Advanced Preliminary
Rev 3
3.1 Added 333 and 400 MHz speed 3.2 Added lead-free and RoHS notes
12-04
Preliminary
Rev 4
4.1 Updated AC, IDD & CAP specifications 4.2 Corrected Mo drawing 4.3 Added lead-free and RoHS note 4.4 Added source control options 4.5 Added industrial temperature option
2-05
Preliminary
Rev 5
5.1 Added JEDEC Standard (JD3) Package Option 5.2 D3 Not Recommended For New Designs
5-05
Preliminary
May 2005 Rev. 5
11
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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